1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) system for synchronizing a feedback clock signal with a reference clock signal, and particularly, to a PLL system for driving a DC motor or a Hall motor.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an analog PLL system 100 according to a prior art. Components of the PLL system 100 will be explained. An oscillator 101 generates a reference clock signal CF. A converter 103 detects the phase difference between the signal CF and a feedback clock signal CB supplied from an input terminal 102 and converts the phase difference into a voltage. A converter 104 detects the frequency difference between the signals CF and CB and converts the frequency difference into a voltage. The converters 103 and 104 form a PLL block. The converter 103 has a phase comparator 103a and a digital-to-analog (DA) converter 103b. The phase comparator 103a converts the phase difference between the signals CF and CB into a binary value, and the DA converter 103b converts the binary value into an analog voltage. The converter 104 has a frequency comparator 104a and a DA converter 104b. The frequency comparator 104a converts the frequency difference between the signals CF and CB into a binary value, and the DA converter 104b converts the binary value into an analog voltage. The output voltages of the converters 103 and 104 are supplied to a PWM signal generator 106 through a loop filter 105. The PWM signal generator 106 compares these output voltages with a triangular wave of optional amplitude and provides a PWM (pulse width modulation) signal. The PWM signal is supplied to an output terminal 107. The loop filter 105 consists of external resistors and capacitors (not shown) that set the loop gain of the PLL system 100. The resistance and capacitance of these resistors and capacitors are determined according to experimental data. The output terminal 107 is connected to a bridge controller 201 for controlling a direct-current (PC) motor 202. The DC motor 202 is connected to a frequency divider 203, which provides the feedback clock signal CB representing the rotational speed of the motor 202.
When the reference clock signal CF is changed, the feedback clock signal CB must be synchronized with the signal CF. For this purpose, the phase comparator 103a and frequency comparator 104a convert the phase difference and frequency difference between the signals CF and CB into binary values. The DA converters 103b and 104b convert the binary values into analog voltages. A combination of the analog voltages is passed through the loop filter 105 and is converted into a PWM signal by the PWM signal generator 106. According to the PWM signal, the controller 201 drives the DC motor 202, and the frequency divider 203 provides the feedback clock signal CB representing the rotational speed of the DC motor 202. These processes are repeated to synchronize the signal CB with the signal CF.
The analog PLL system of the prior art has the following problems:
(1) The reference and feedback clock signals CF and CB must be converted into binary values by the phase comparator 103a and frequency comparator 104a, then into analog voltages by the DA converters 103b and 104b, and into a PWM signal by the PWM signal generator 106. Namely, the prior art involves three signal conversion processes to complicate the structure of the PLL system, and requires long processing time for providing an output signal.
(2) The PLL system must have the loop filter 105 consisting of external resistors and capacitors. This configuration limits the range of loop gains to be set, since the ripple magnitude manifested on the output waveform of the loop filter 105 increases lineally with the loop gain.